It is a common practice to integrate memory and logic functions on a common semiconductor substrate. In such a configuration, when the memory function is performed by a dynamic random access memory (DRAM) cell, the circuitry is referred to as embedded DRAM (eDRAM).
The use of eDRAM as microprocessor cache, however, involves making tradeoffs between performance parameters, such as speed, retention time and power consumption, and production parameters, such as yield and design complexity. Due to their small sizes, memory cells are especially susceptible to process-induced variations, which worsen these tradeoffs and compromise memory cell functionality. Thus, steps need to be taken to minimize process-induced variations.
For example, reducing variability in the pass transistor of an eDRAM cell can simultaneously improve all memory cell performance parameters. Typically, an eDRAM cell calls for a bulk-silicon pass transistor with a heavily doped channel which, in addition to being sensitive to process non-uniformities, is inherently vulnerable to variability from random dopant fluctuations. See, R. W. Keyes, “Effect of Randomness in the Distribution of Impurity Ions on FET Thresholds in Integrated Electronics,” IEEE Journal of Solid-State Circuits, vol. SC-10, pp. 245-247, August 1975. While solutions for addressing variability problems in microprocessor memories exist to better control device characteristics (e.g., better process control during manufacturing and careful cell layout), random dopant fluctuations present a fundamental limitation to improving eDRAM performance.
The use of undoped channel devices such as fin-field effect transistors (FinFETs) for memory (both static random access memory (SRAM) and DRAM) has been proposed for this reason. See, R. Katsumata et al., “Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM,” Symposium on VLSI Technology, 2003; M. Yoshida et al., “A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique,” Symposium on VLSI Technology, 2006; and H. Kawasaki et al., “Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond,” Symposium on VLSI Technology, 2006. However, the integration of FinFETs with planar logic is difficult due to vertical topography, especially since DRAM processes generally rely on bulk silicon wafer substrates. In addition, an entirely FinFET-based technology (both memory and logic) has yet to be implemented in the industry. Thus, the use of FinFETs for eDRAM is not yet practical. Currently, the standard approach in modern memory technologies has been to use larger devices for memory than for logic at the expense of layout density.
As such, techniques that eliminate variability due to random dopant fluctuations in eDRAM would be desirable.